Fault-tolerance techniques for sram-based fpgas pdf merge

However, specific techniques are required to enhance the dependability of solutions running on fpgas. Systemc language reference manual was published early in 2012 iee12. Hybrid time and hardware redundancy to mitigate seu effects. As the adverse effects of radiations in space are much higher than in the earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. The configuration memory cells are however susceptible to ionised particles which upon impact can cause the memory cell to change state. This article presents a fault tolerance technique for transient and permanent faults in srambased fpgas. It starts by showing the model of the problem and the upset effects in the programmable architecture. This thesis is about managing srambased fpga faults at system level, in the context of. Fpgas, static random access memory sram is the dominant technology used for the configuration bits. Sram based fpga sram bits can be programmed many times each programming bit requires 5 or 6 transistors khbo presentation 27 november 2012 10 read or write data q q programming bit interconnection i1i2 p1 p2 p3 p4 out 2input lut lut ref 5. This approach solves the mismatch problem which happens in the process of synthesis. A large set of methods for designing fault tolerance systems in srambased fpgas is described.

Fpga, reconfigurable fault tolerance, singleevent upsets. Inputoutput logic based faulttolerant design technique for srambased fpgas aditya srinivas timmaraju, deshmukh aniket anand, mohammed amir khan, zafar ali khan abstracteffects of radiation on electronic circuits used in extraterrestrial applications and radiation prone environments need to be corrected. Reliabilityaware placement in srambased fpga for voltage. Designing faulttolerant techniques for srambased fpgas article pdf available in ieee design and test of computers 21. Fault tolerance implementation within sram based fpga designs. This book examines faulttolerance techniques for srambased fpgas, beginning with modeling of the problem and the upset effects in. A survey on design standards and proposed methodologies cinzia bernardeschi 1, luca cassano 2. Data analysis and results of the radiationtolerant. This technique combines duplication with comparison dwc and. A highlevel synthesis scheduling and binding heuristic for. Aug 08, 2016 fault tolerance within sram based fpgas for aerospace applications abstract. Srambased fpga systems for safetycritical applications. This book discusses fault tolerance techniques for sram based field programmable gate arrays fpgas. During the last three decades, reconfigurable logic has been growing steadily and can now be found in many different fields.

Some presented techniques are based on developing a new faulttolerant architecture with new robustness fpga elements. Pdf designing faulttolerant techniques for srambased fpgas. Soft error rate estimation and mitigation for srambased. Sram based field programmable gate arrays fpgas are particularly sensitive to single event upsets caused by highenergy space radiation. Fpga architecture support for heterogeneous, relocatable partial bitstreams. Sram based fpgas allow engineers to perform product improvements by rewriting the configuration data. They often do not execute the scrubbing process in the right instant. However, fault tolerance techniques might introduce addi. Soft error rate estimation and mitigation for srambased fpgas. Designing fault tolerant systems into srambased fpgas. Rollins department of electrical and computer engineering doctor of philosophy softcore processors are an attractive alternative to using expensive radiationhardened processors for space based applications. However, aggressive voltage scaling causes processvariation. Although effective, tmr suffers from a 3x area overhead, which can be prohibitive for many embedded usage scenarios. Explores classical fpga architectures and their supporting tools.

Assessing scrubbing techniques for xilinx srambased fpgas in space applications fredrik brosser, emil milh, vilhelm geijery, and per larssonedefors dept. The reprogranmability of sum based fpgas enables the use of multiple mission. Reducing tmr overheads by combining hardware and time redundancy. Assessing scrubbing techniques for xilinx srambased fpgas in. This paper proposes an improvement test approach of lookup table in sram based fpgas from the thirdparty testing. Single event upset in order to successfully deploy the sram fpga based designs in aerospace applications, designers need to adopt suitable hardening techniques. Faulttolerance techniques for srambased fpgas request pdf. Among the fault tolerance characteristics, the performance and costs of an electronic system remain the leader factors in the space and avionics market.

The goals of the fault tolerance techniques are to minimize the hardware, timing, and power overhead, and maximize the reliability of the system. Fpgabased highperformance embedded systems for adaptive. Inputoutput logic based faulttolerant design technique. This book examines fault tolerance techniques for sram based fpgas, beginning with modeling of the problem and the upset effects in the programmable. There are two ways to implement faulttolerant circuits in srambased fpgas. Designing and testing faulttolerant techniques for sram. Proceedings of the ieee 23rd international symposium on online testing and robust system design. Faulttolerance techniques for srambased fpgas fernanda. However, the current scrubbing techniques execute without considering the criticality and timing of the user tasks implemented in the fpga. Therefore, voltage scaling on the srams can be an effective solution for lowering the power consumption in the configuration memories of fpgas. These features allow sram based fpgas to address resource multiplexing, fault tolerance, mission obsolescence and design flaws in onorbit payloads that drectly impact design cost and mission risk, while also providing better processkg performaxe. Furthermore, this overhead is often worsened because tmr often has to be applied to. Srambased fpgas has made it possible to incorporate fault tolerance into. Request pdf designing and testing faulttolerant techniques for srambased fpgas this paper discusses faulttolerant techniques for srambased fpgas.

Section 2 describes how softerrors corrupt the operation of sram based fpgas. Fault tolerance is the ability of a system to operate normally given the presence of malfunctioning resources, faults or defects. Faultmitigation strategies for reliable fpga architecture. These features allow sram based fpgas to address resource multiplexing, fault tolerance, mission obsolescence and design flaws in onorbit payloads that directly impact. Hardware and software faulttolerance of softcore processors. Assessing scrubbing techniques for xilinx srambased. On the optimal design of triple modular redundancy logic for sram based fpgas f. This work presents a real case of a satellite, optos cubesat, designed, manufactured, launched, and flight during a 3year mission that merge the new winds of flexibility, smart fault tolerance techniques, and cost consciousness to prove it is possible to produce reliable and effective architectures for small satellites.

Abstractrecently, srambased fpgas are widely used in aeronautic and space systems. Other techniques are based on protecting the highlevel hardware description before the synthesis in the fpga. However, new semiconductor manufacturing technologies increase the probability of lifetime operation failures, requiring new online testing fault tolerance methods able to improve the dependability of the systems where they are included. This technique combines duplication with comparison.

Fpgas can be seen as arrays of logic units that can be recon. However, most commercial fpgas, due to their general purpose architectural nature, cannot handle. In the sequence, it shows the main fault tolerance techniques used nowadays to protect integrated circuits against errors. Fault tolerance designing faulttolerant techniques for. Criticalityaware scrubbing mechanism for srambased fpgas. Field programmable gate arrays fpgas are one of the most famous architecture families of reconfigurable devices. The active replication technique presented in this. Covering a broad range of architectures, tools, and applications, this book. Triple modular redundancy tmr has been successfully applied in fpgas to mitigate transient faults, which are likely to occur in space applications. Fpga architecture support for heterogeneous, relocatable. Computing systems with fieldprogrammable gate arrays fpgas often achieve fault tolerance in highenergy radiation environments via triplemodular redundancy tmr and configuration scrubbing. Design tools for reconfigurable hardware orbit rhino. A novel design flow for fault tolerance srambased fpga systems. Designing faulttolerant techniques for srambased fpgas.

Fis, a bitstream download can be affected by radiation effects, potentially. Inputoutput logic based faulttolerant design technique for. Many applications can accept these limitations, but some cannot. Semantic scholar extracted view of faulttolerance techniques for srambased fpgas by ricardo p. Design tools for reconfigurable hardware in orbit rhino. An improvement test approach of lookup table in srambased fpgas. Request pdf faulttolerance techniques for srambased fpgas faulttolerance in integrated circuits is no longer the exclusive concern of space designers or highlyreliable applications engineers. Designing and testing faulttolerant techniques for srambased. Seu fault evaluation and characteristics for srambased fpga. This paper discusses high level techniques for designing fault tolerant systems in sram based fpgas, without modification in the fpga architecture. On the design of tunable fault tolerant circuits on sram. In this regard, the runtime reconfiguration capabilities available in sram based fpgas, which enable the timemultiplexing of computing resources, make them appropriate for the adaptability levels required by cpss.

Semantic scholar extracted view of faulttolerance techniques for sram based fpgas by ricardo p. A defecttolerant areaefficient multiplexer for basic blocks in sram based fpgas author links open overlay panel a. Fault tolerance within sram based fpgas for aerospace. Assessing scrubbing techniques for xilinx sram based fpgas in space applications fredrik brosser, emil milh, vilhelm geijery, and per larssonedefors dept.

Online testing and recovery of systems on srambased fpga. Improving autonomous softerror tolerance of fpga through lut. In particular, when considering sram based fpgas, specific hardening techniques generally based on. The first possibility is to design a new fpga matrix composed of faulttolerant elements. A possible solution is to combine the temporal latch composed of. Static random access memory sram based fpgas are now common in space based systems research such as that on the reconfigurable hardware in orbit rhino nasa aist03 project developed radiation hardening by software rhbsw techniques to mitigate single event upsets in commercial grade devices cots. Key contributions in this respect are the following. A generic methodology to compute design sensitivity to seu in. Electronics system design techniques for safety critical applications. Architecture, tools, and applications offers a snapshot of the state of the art of reconfigurable logic systems.

Hardware and software fault tolerance of softcore processors implemented in sram based fpgas nathaniel h. A faulttolerant system for a srambased fpgas, must cope with the transient and permanent effects of an seu in the combinational logic, short and open circuits in the design connections, and bit. With increased logic density due to the shift towards deep submicron technologies dsm, fpgas have become a viable option for implementing large designs. Fault tolerant techniques for reconfigurable devices international. Fpgas have become prevalent in critical applications in which transient faults can seriously affect the circuits operation. This paper discusses faulttolerant techniques for srambased. Fault tolerant technique based on dwc combined with ced for srambased fpgas. A defecttolerant areaefficient multiplexer for basic blocks. This paper discusses high level techniques for designing fault tolerant systems in srambased fpgas, without modification in the fpga architecture.